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嵌入式OS--4G手機(jī)操作系統(tǒng)

手機(jī)/網(wǎng)絡(luò)/動(dòng)漫游戲開發(fā)

嵌入式OS--WinCE

單片機(jī)培訓(xùn)

嵌入式硬件設(shè)計(jì)

嵌入式OS--VxWorks

PowerPC嵌入式系統(tǒng)/編譯器優(yōu)化

3G手機(jī)軟件測(cè)試、硬件測(cè)試

云計(jì)算、物聯(lián)網(wǎng)

開源操作系統(tǒng)Tiny OS開發(fā)

其他類

　

　

公益培訓(xùn)通知與資料下載

端海招聘啟示

　　培訓(xùn)班最新動(dòng)態(tài) 　

　　Silicon-package-board co-design培訓(xùn)

第一階段 Allegro AMS Simulator

Course Description

The Allegro? AMS Simulator course starts with the basics of entering a design for simulation and builds a solid foundation in the overall use of the software. You run DC Bias simulations, transient analysis simulations, and sweep simulations, allowing you to sweep component values, operating frequencies, or global parameters. You also have the opportunity to simulate several types of analog circuits, transformers, digital circuits, and mixed analog and digital circuits.

Learning Objectives

After completing this course you will be able to:

• Enter a design for simulation
• Run DC bias, DC sweep, and AC sweep analyses
• Edit a stimulus and run a parametric analysis
• Edit models, run a Monte Carlo analysis, create subcircuits, and create parts for simulation from a model or subcircuit definition
• Create linear and non-linear transformers, and perform temperature, worst-case, and noise analysis
• Apply analog behavioral modeling and run digital and mixed analog and digital simulation

Course Agenda

Note that this course can be tailored to better meet your needs?–?contact the Cadence training staff?for specifics.

Unit 1

• Building a design for simulation
• Setting up and running DC bias point analysis
• Setting up and running DC and AC sweep analyses
• Viewing simulation results in the probe window
• Setting up sources and using markers
• Creating and simulating a text netlist
• Accessing the stimulus editor using VSTIM, ISTIM, and DIGSTIM Running transient analysis

Unit 2

• Examining common simulation errors
• Creating linear and non-linear transformers
• Setting up and running parametric analysis
• Creating a subcircuit
• Performing temperature analysis
• Configuring and running Monte Carlo analysis
• Simulating with hierarchical blocks and symbols

Unit 3

• Running simulations using analog behavioral modeling
• Using digital components in a design
• Combining analog and digital components in designs
• Using performance analysis and creating goal functions
• Setting up and running worst-case analysis
• Setting up and running noise analysis

第二階段 Allegro Design Entry HDL Front-to-Back Flow

Course Description

In this course, you create board-level schematic designs with Design Entry HDL. You explore the integration between Design Entry HDL and other tools in the design flow, including the Allegro? PCB Editor. You follow the design flow by creating a schematic and taking it all the way through board layout.

Although board layout is introduced as part of the front-to-back flow, this is not a board layout course. Also, schematic or footprint library development is not included in this course. See the Related Courses below.

Learning Objectives

After completing this course, you will be able to:

• Set up new projects
• Create a flat, multisheet design
• Check the design
• Use part tables
• Package a design
• Create and customize a bill of materials
• Build a hierarchical design
• Use schematic properties to control part placement
• Use the Constraint Manager to define high-speed routing requirements in Design Entry HDL
• Transfer the design to the PCB Editor
• Place parts manually
• Autoroute with the PCB Router
• Compare the schematic and layout
• Synchronize design differences
• Incorporate engineering changes
• Link projects together in a team-design scenario
• Reuse a hierarchical block and associated layout in another design

Course Sessions

Note that this course can be tailored to better meet your needs –?contact the Cadence training staff?for specifics.

Session 1

• Getting Started
• Project Setup

Session 2

• Design Entry and Packaging

Session 3

• Hierarchical and Team Design

Session 4

• Design Rules
• Rules-Driven Layout

Session 5

• Engineering Changes